1. Field of the Invention
The present invention relates to a PC card controller having advanced power management and register reset capabilities. More particularly, the present invention relates to a PC card controller that support register reset capabilities for advanced power management modes. Particular utility of the present invention is a cardbus controller supporting advanced power management capabilities for a plurality of expansion cards for portable computer devices; although other utilities are contemplated herein.
2. Description of Related Art
Conventionally, prior to power management specifications, PCI devices in portable notebook computers supported the following power states: (1) power on state, (2) power off state, (3) low power (sleep) state accomplished by turning off internal clock signals and (4) a suspended state by powering off most of the system power. However, this approach has numerous limitations. For example, a device which has an internal clock (for example, an internal PLL generated clock) may take an extended time to bring the clock back on to a powered state before the device can be accessed. Also, since the operating system (OS) normally has no data about the status of various devices, the OS may falsely interpret the timed out device as failed. FIG. 1 depicts conventional registers 12, 14 and 16 of a conventional Cardbus controller 10. Conventional registers include: PCI configuration registers 12 that provide interface information between the controller 10 and a PCI bus, Cardbus control registers 14 that generate internal instructions and commands for cardbus control, and proprietary registers 16 (implemented by the specific design manufacturer of the controller which may include general I/O registers, specific pinout registers, etc.). In the conventional controller 10, a PCI reset signal is used to reset registers 12, 14 and 16. In conventional cardbus controllers, numerous cardbus devices could not be put into a power saving mode at all since these controllers do not support power management specifications.
To remedy these defects, Microsoft Corporation defined a series of protocols known as the ACPI (Advanced Configuration and Power Interface Specifications). Likewise, the PCI committee defined the PCI power management specification to tackle these problems. To be harmonious with the specifications, the PCMCIA committee (also based on the PCI power management specification) defined the cardbus power management specification so that most of the PCI devices (including cardbus controllers) used in portable computers are modified to adapt advanced power management specifications.
In the PCI power management specification, the PCI bus is defined into D0, D1, D2, D3_HOT and D3_COLD states. Legacy PCI devices typically automatically support D0 (power on) and D3_COLD (power off) states. The D1, D2 and D3_HOT states are varying levels of power saving states advanced under these specifications. In general, the D1 states consumes less power than the D0 state, the D2 state consumes less power than the D1 state, and so on. Included in the PCI power management specifications is a new power supply, commonly known as AUXVCC which is added in the D3_COLD state. The AUX VCC is a new power definition which can be used to maintain certain logic when the main source, known as PCI VCC, is in an off state. Thus, AUX VCC was added to maintain certain logic at a predefined minimum value while permitting the rest of the system to be turned off. To maintain certain information in certain registers, AUX VCC supplies power to these registers to permit wake up and identification when the system is switched from D3_COLD state to D0 state. To properly wake up the system from a D3_COLD state back to a D0 state, some of the power management and proprietary registers need to maintain data therein to instruct the operating system properly, so that upon a wake up command the operating system can identify which device has instructed a wake up.
When the controller receives a request to wake up from the D3_COLD state back to the D0 state, the AUX VCC signal permits the appropriate power management registers to remain active and process this request. Thus, the operating system receives the proper information from the devices seeking this request. In conventional cardbus controllers, the power management and proprietary registers block system resets when the requesting devices goes from a D3_COLD state (to another state) by checking the power state registers. However, if the system is powered up from a total power off state, cardbus devices have difficulty determining whether the data contained in the power state registers are correct, or just random values. A typical example in the cardbus controller is the cardbus socket power registers. Since there are different types of PC cards, and if the socket power is not initialized correctly, the controller may erroneously apply a 5 volt power to a 3 volt card, which can damage the card before the bios determines the error. Thus, there is a recognized need to properly reset the power management and proprietary registers when the system is powered up from a total power off state.
The simplest way to accomplish a power up reset would be to provide an additional pin on the controller and use that as a global reset of the appropriate registers. However, this requires a pin assignment change. Given the vast amount of installations of cardbus controllers in computer systems, this would be an undesirable fix since it would require wiring and tooling changes to accommodate the additional pin. Moreover, cardbus controller technology is a mature technology, and different manufacturers implement different pin configurations and most of the pins are multiplexed to perform different functions so that pin out arrangements are at a minimum. Thus, there is a need to provide a cardbus controller that includes power on reset capabilities to reset the PCI and cardbus power management registers and proprietary registers without any changes in pin assignments or wiring layouts.